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Century Semiconductor Inc.
GENERAL DESCRIPTION CS8552 provides full conversion from digital video format YCbCr into NTSC/PAL composite and Svideo. It can be used in VCD, DVD, digital VCR application. Two-times oversampling reduces the output filter requirements and guarantees no alias interference by internal UV filters and Y filter. Two 9-bit DACs provides two channels for a Svideo output port or two composite video outputs with high quality of image. 32-pin package and pin assignment make CS8552 compatible with major vendors. FEATURES
CS8552 TV Encoder
BLOCK DIAGRAM
HOL
CONTROLLER SERIAL TO 4:2:2 to 4:4:4 PARALLEL INTERPOLATION VBIAS VREF_O
H, V-SYNC
VIDEO-TIMING
PL
SUB-CARRIER GENERATION SINE-TABLE u-FILTER v-FILTER COLOR-BURST & MODULATION & MIXER CVBS/Y CVBS/C y-FILTER DACMAPPING FSADJUST COMP
CLK_27 SLEEP
P[7:0]
MODE[3:0] SVIDEO MASTER CBSWAP
Century Semiconductor, Inc. Taiwan: No. 2, Industry East Rd. 3rd, Science-Based Industrial Park, Hsin-Chu, Taiwan Tel: 886-3-5784866 Fax: 886-3-5784349
3U
QD
* Designed special for VCD, Karaoke, digital VCR, DVD, DIGITAL set-top box. * Support the following 4 modes: NTSC, PAL-M, PAL-BDGHI, PAL-Nc * 8-bit 4:2:2 YcbCr inputs for glueless interface to MPEG decoders * CVBS (composite YC) or S-video (Y and C) outputs * Support CCIR-6-1 for mat, non-square pixel * 2x oversampling simplify external filtering * 6MHz and 1.3MHz anti-alias filters for Y and U/V channels each * On-chip color bar generation * 2 channels of 9-bit DAC * Support master and slave modes * Support interlace operation only * Automatic mode detection/switching in slave mode * 3.3V supply voltage; 5V tolerant for all digital I/O pins
USA: 1485 Saratoga Ave. #200 San Jose, CA, 95129 Tel: 408-973-8388 Fax: 408-973-9388
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Sales@century-semi.com Sales@century-semi.com.tw www.century-semi.com Rev.0.1 May 2001 page 1 of 23
Century Semiconductor Inc.
PIN CONNECTION DIAGRAM
CS8552
CLK_27M
P7
P6
P5
P4
P3
P2
P1 22
29
28
27
26
25
24
23
21
P0
VSS VDD VSYNC HSYNC NC VSS CVBSY
30 31 32 1 2 3 4
20 19 18 17 16 15 14
MD0 MD1 MD2 MD3
CS8552
QD PL
10 12 CVBSC VDD 11 6 7 8 9 VBIAS VSS COMPI
3U
HOL
Figure-1 32-pin PLCC
VREFO
SLEEP
FADJI
VREFI
13
5
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MASTERI CBSWAPI SVIDEOI page 2 of 23
Century Semiconductor Inc.
PIN DESCRIPTION
Name CLKI VSYNC HSYNC P[7:0] I/O I I/O I/O I Pin 29 32 1 28-21 Description Pixel clock, 27MHz, twice the Y sample rate
CS8552
Vertical sync, output in master mode or input in slave mode, is synchronized by CLK. Horizontal sync, output in master mode or input in slave mode, is synchronized by CLK too. YCbCr pixel inputs (TTL compatible). Also, synchronized by CLK with respect to the incoming HSYNC timing, the higher index corresponds to a greater significance. Configuration inputs in 0: slave mode, h and v sync are inputs. 1: master mode, h and v sync are outputs. 0: normal Cr, Cb sequence. 1: swaps Cr, Cb sequence 0: composite output same signal on both Y, C channels, 1: s-video output, Y, C channels. 1: power down, reset 0: normal operation
MD[3:0] MASTER CBSWAP SVIDEO SLEEP FSADJUST COMP VREFO VREFI/VRDAC
I I I I I I I I I
17-20 16 15 14 13 5 6 8 9
Full scale adjust control pin. A resistor is connected to GND. Used to control the full-scale output current on analog outputs. Compensation pin. A 0.1F capacitor is used to bypass this pin to VCC. Voltage reference output, typically 1.2V, may be used to connect to VREFI input.
VBIAS CVBS/C CVBS/Y VAA VDD GND AGND NC
O O O
10 11 4
3U
3, 12 2
HOL
7 Analog power 31 Digital power 30 Digital ground Analog ground No connection
PL
Voltage reference input, typically 1.235V. A 0.11F capacitor must be used to decouple this input to GND. DAC current switch reference input, connect to VREFO output. DAC bias voltage, 0.7 v less than COMP signal
Composite output or chrominance Composite output or luminance (with blanking and sync)
QD
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page 3 of 23
Century Semiconductor Inc.
FUNCTIONAL DESCRIPTION MODE configuration SeeTable 1 to Table 3 for details. master = 1: master mode
CS8552
horizontal sync and vertical sync are generated from internal timing and are output at the rising edge of clk_27. md[3]: define EFIELD function 0: vsync is output pin 1: vsync is even/odd field indicator, vsync=0 even, vsync=1 odd. md[2]: define PAL625 function 0: 525 line operation is set. 1: 626 line operation is set. master = 0: slave mode Horizontal sync and vertical sync are inputs that are synchronized by clk_27. A falling edge of VSYNC* occurring within 1/4 of a scan line from the falling edge of HSYNC* cycle time indicates the beginning of Field-1. A falling edge of VSYNC* occurring within 1/4 of a scan line from the middle point of the line indicates the beginning of Field-2. See Figure 2
Field-1
md[3]: define YCSWAP 0: normal operation. 1: Swap the luma and chroma samples. md[2]: define SETUP function 0: 7.5 IRE setup is enabled for NTSC and PAL-M, with scaling for 92.5% black-to-white range, other PALs with normal 100% black-to-white range. 1: 7.5 IRE setup is disabled for NTSC and PAL-M, with scaling for 100% black-to-white range. md[1]: define PALSA function, South America. 0: Normal operation. 1: PAL-M used for Brazil 525 lines operation. PAL-Nc used for Argentina 625 lines operation.
3U
HOL
PL
Figure-2
page 4 of 23
QD
Field-2
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Century Semiconductor Inc.
Table-1 Mode Slave Master EFIELD PAL625 YCSWAP SETUP Mode[3] YCSWAP EFIELD Mode[2] SETUP PAL625 Mode[1] PALSA RESERVED
CS8552
Mode[0] RESERVED RESERVED
PALSA
Table-2 master
1 1 1 1
Master mode: Mode[3:0] X000 X010 X000 X010 X000 X110 X010 X110
PL
0 1 1 PAL-625 0 0 1 1
System (Normal setup) NTSC PAL-M PAL-BDGHI PAL-Nc
QD
PAL-625 0
EFIELD is used when configured as a master. When EFIELD is set low, the Normal vsync* signal is output on the VSYNC* pin. When EFIELD is set high, field ID information is output on the VSYNC* pin (VSYNC* low for Field-1 and high for Field-2) PAL625 is used when configured as a master. When PAL625 is set low, 525-line operation is selected. When PAL625 is set high, 625-line operation is selected. This mode is set by automatic detection when configured as a slave. YCSWAP should normally be set to zero. When configured as a slave, this bit can be set high to swap the luma and chroma samples, thus altering the pixel sequence with respect to the incoming HSYNC* timing reference. SETUP is normally low for the common video modes. The setup and scaling function is toggled when this bit is high. When SETUP is low, the 7.5IRE setup is enabled for NTSC and PAL-M with scaling amplified for a 92.5% black-to-white range; other PAL formats have setup disabled with normal 100% scaling. When SETUP is high, the 7.5 IRE setup is disabled for NTSC and PAL-M with 100% black-to-white range scaling; other PAL formats have setup enabled with amplified scaling. PALSA is normally low for the common video modes. South American video Standards can be enabled by setting this bit high. For 525-line operation, the PALSA enables PAL-M for Brazil; in 625line operation, the PALSA enables PAL-Nc for Argentina.
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PALSA 0 1 0 1 PALSA 0 1 0 1
Fv Hz 59.94 59.94 50.00 50.00
Fh Hz 15734.26 15734.26 15625 15625
Table-3 Master 0 0 0 0
Slave mode:
3U
Mode[3:0] X000 X010 X000 X010
HOL
System NTSC PAL-M PAL-BDGHI PAL-Nc
Fv hz 59.94 59.94 50.00 50.00
Fh Hz 15734.26 15734.26 15625 15625
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Century Semiconductor Inc.
CS8552
PIXEL INPUT/OUTPUT TIMING 1. clk is 2x the luminance sampling rate (13.5 MHz) or 4x the chrominance sampling rate (6.75 MHz), all signals are reference to rising edge. 2. In accordance with CCIR656, the input pixel pattern begins during the first clk period after the falling edge of HSYNC (same for master mode and slave mode). The input pattern is Cb0, Y0, Cr0, Y1, Cb2, Y2, Cr2, Y3,...... The input pin CBSWAP and md[3] (YCSWAP) could be used to swap cb, cr sequence and also y and cb, cr sequence. See Figure 3. 3. Pixel input range: See Table 4 Y: 16-235 for normal range; 0-15, 236-255 are invalid. When Y value is between 0-15 then clamp to 16, when 236 and 255 Y will be set to 255. CbCr: 16-240 for normal range with 128 mapped to 0; 0-15, 241-255 are invalid. When Cb/Cr is between 0-15 will be clamp to 16, when Cb/Cr is 241 to 255 then will be set to 240. Table-4
Y Cb Cr
75% amplitude, 100% saturated YCbCr color bars range
16-235 16-240 16-240
element
White
235 128 128
Yellow
162 44 142
Cyan
131 156 44
Green
112 72 58
Magenta
84 184 198
Red
65 100 212
Blue
35 212 114
black
16 128 128
CLK HSYNC*
YCSWAP=0 P[7:0]/CBSWAP=0 P[7:0]/CBSWAP=1 YCSWAP=1 P[7:0]/CBSWAP=0 P[7:0]/CBSWAP=1
PL
cb0 cr0 y0 cr0 y1 cb2 cr2 y0 cb0 y1 y0 cb0 cr0 y1 cr2 y2 y2 y0 y1 cb1
QD
y2 y2 cr2 cb2 y3 y3 cb4 cr4 cb2 cr2 y3 y3 cr4 cb4 y4 y4
3U
HOL
Figure-3
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page 6 of 23
Century Semiconductor Inc.
VIDEO TIMING See Table 5, Table 6
CS8552
1. If master mode is selected, horizontal counter is incremented on clk/2, and reset to 1 when h-total is hit. The output hsync is 6 clk later than the internal horizontal sync. Vertical counter is incremented by every horizontal scan line and reset to 1 after v-total hit. The output vertical sync is 3 or 2.5 lines for 262/525 and 312/625 later. 2. If slave mode is selected, the horizontal counter is incremented on the rising of clk and then reset to 1 after 2 clk cycles late of falling edge of hsync. The vertical counter is incremented on the falling edge of hsync and reset to 1 at falling edge of vertical sync. If the falling edge of vertical sync occurring within [-1/4,1/4] of a scan line from the falling edge of hsync indicates the even field, if within [-1/4,1/4] of middle point of scan line indicates odd field. 3. The width of horizontal sync and the start and end of color burst is automatically calculated and inserted for each mode. 4. sync timing and burst envelopes are internally controlled. Color burst frequency is derived from the clk. Any jitter on clk may induce a color burst frequency error. 5. timing tables: Table-5 System
NTSC PAL-BDK.
Vertical timing table Odd-field Non-active Odd-field Active
Line 1-22 VBI=7-21 Line 1-22 VBI=7-21 Line 23-262 Line 23-310
Even-field Non-active
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Even-field Active
Line 285-524 Line 336-623
Total size
Active size
720*480 720*576
QD
Active
711 711 702 702
Line 263-284; 525 VBI=270-284 Line 311-335; 624, 625 VBI=319-333
858*525 864*625
Table-6 System
NTSC PAL-M PAL-BD.. PAL-Nc
Horizontal timing table: number of 13.5 MHz cycles Front-porch
20 20 20 20
Back-porch
127(122) 127 142(132) 142
PL
Burst-start
72 78 76 76
Burst-width
34 34 30 34
total
858 858 864 864
3U
6. Color burst is disabled on appropriate scan lines. Serration and equalization pulses are generated on appropriate scan lines. For NTSC, color burst information is automatically disabled on scan line 1-9 and 264272 or PAL-M, color burst information is automatically disabled on scan line 1-11 and 263-273. For PALBDGHINc, color burst information is automatically disabled on scan line 1-6 and 310-318 and 623-625 for field 1,2,5,6. However, for field 3,4,7,8 burst is disabled at scan line 1-5,311-319,622-625. See the following Figure 4, Figure 5 and Figure 6.
HOL
page 7 of 23
Century Semiconductor Inc.
CS8552
Analog field-1
Start of vsync
525
1 2 (equalization)
3
4 (serration) burst phase
5
6
7 8 (equalization)
9
10
262
263
264
265
266
267
QD
268 269 270 5 6 7 8 268 269 270
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271 272 273 3
Analog field-2
Analog field-3
525
1
2
PL
4 burst phase 266 267
9
10
Analog field-4
Burst begins with positive half-cycle Burst phase=reference phase=180 relative to B-Y Burst begins with negative half-cycle Burst phase=reference phase=180 relative to B-Y
3U
262
263
264
HOL
265
271
272
273
Figure-4 Interface 525-line (NTSC) video timing
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Century Semiconductor Inc.
Start vsync Analog field-1
CS8552
621 622
623
624
625
1 -U phase Analog field-2
2
3
4
5
6
7
309
310
311
312
313
314
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315 316 317 318 2 3 4 5 6 315 316 317 318
319
320
Analog field-3
621 622
623
624
625
1
QD
314
7
Analog field-4
309
310
311
312
PL
313 field-1 field-2 field-3 field-4
319
320
3U
Burst phase=reference phase=135 relative to U; PAL switch=0, +V component Burst phase=reference phase + 90=225 relative to U; PAL switch=1, -V component
Figure-5 Interface 625-line (PAL-B,D,G,H,I,N,Nc) video timing
HOL
page 9 of 23
Century Semiconductor Inc.
Start vsync Analog field-5
CS8552
621 622
623
624
625
1 -U phase Analog field-6
2
3
4
5
6
7
309
310
311
312
313
314
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315 316 317 318 2 3 4 5 6 315 316 317 318
319
320
Analog field-7
621 622
623
624
625
1
QD
314
7
309
310
311
312
PL
313 field-5 field-6 field-7 field-8
Analog field-8
319
320
3U
Burst phase=reference phase = 135 relative to U; PAL switch=0, +V component Burst phase=reference phase + 90 = 225 relative to U; PAL switch=1, -V component
HOL
Figure-6
page 10 of 23
Century Semiconductor Inc.
ANTI-ALIAS FILTERS CHARACTERIS
CS8552
The Y and the U, V are up-samples to clk, 27MHz after 4:2:2 to 4:4:4 conversion. Y is filtered by a filter whose passband is 6MHz. And U, V are also filtered by passband = 1.3MHz filters. Please refer to Figure 7 to Figure 10
Db 0
-1
-2 -3 0 2 4 6
Figure-7 2X Sample Y filter frequency response/passband
Db
0 -10 -20
3U
-55 0 2 4
-40
HOL
6 8 10 MHz Figure-8 2X Sample Y filter frequency response/stopband
page 11 of 23
PL
QD
U\
8 MHz
Century Semiconductor Inc.
Db 0
CS8552
-1
-2 -3 0 2 4 6
Figure-9 2X U/V filter frequency response/passband
Db
0 -10 -20
-40 -55 0
HOL
0.5 1 1.5
PL
2 2.5 MHz Figure-10 2X U/V filter frequency response/stopband
page 12 of 23
3U
QD
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8 MHz
Century Semiconductor Inc.
DAC MAPPING
CS8552
Depends on the video output mode, the color bars mapping to DAC are specified in Table 7 to Table 12 and Figure 11 to Figure 16. Where white is 400. For PAL-BDGHINc blank = 120. For NTSC/PAL-M blank = 114 (setup = 0), 1 IRE = 2.857; if setup = 1, blank = 112, 1 IRE = 2.8. Table-7
White Black Blank Sync
s-video Y NTSC/PAL-M 525, setup = 0 DAC data
400 136 114 0
Description
Sync interval
0 0 0 1
W mA V 26.68 1.000 400
Y 370
C
100 IRE
PL
QD
321 291 245 215 166 136 114 blank level sync level
page 13 of 23
9.07 7.6
0.34 0.285
7.5 IRE 40 IRE
0.00
0.00
W: white Y: yellow C: cyan G: green M: magenta R: red B: blue
Figure-11 Color bars, s-video Y NTSC/PAL-M 525, setup=0 video output waveform
3U
HOL
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G M R B
Century Semiconductor Inc.
Table-8
White Black Blank Sync
CS8552
s-video Y PAL-BDGHINc 625 DAC data
400 120 120 0
Description
Sync interval
0 0 0 1
Typical with 37.5 load, vref_o = vref_i, SETUP = 0 100% saturation (100/0/100/0) color bars.
W mA V 26.68 1.000 400
Y 368
C
G
M
R
B
319
QD
236 204
PL HOL
8.0
0.30
0.00
0.00
W: white Y: yellow C: cyan G: green M: magenta R: red B: blue
3U
Figure-12 color bars, s-video Y PAL-BDGHINc 625 video output waveform
U\
284 152 120 black/blank level sync level
page 14 of 23
Century Semiconductor Inc.
Table-9 s-video Chrominance NTSC/PAL-M 525 Typical with 37.5 load, vref_o = vref_i, SETUP = 0 100% saturation color bars.
CS8552
Description
Peak C (high) Burst (high) Blank Burst (low) Peak C (low)
DAC data
423 313 256 199 89
Sync interval
No No No No No
mA V 28.21 1.058
20.88 0.783 17.07 0.64 13.27 0.498
QD PL
color-burst
5.93
Figure-13 color bars, s-video Chrominance NTSC/PAL-M 525 video output waveform
3U
HOL
0.222
U\
blank level
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Century Semiconductor Inc.
Table-10 s-video Chrominance PAL-BDGNICc 625 Typical with 37.5 load, vref_o = vref_i, SETUP = 0 100% saturation (100/0/100/0) color bars.
CS8552
Description
Peak C (high) Burst (high) Blank Burst (low) Peak C (low) 433 316 256 196 79
DAC data
No No No No No
Sync interval
mA V 28.88 1.083
21.08 0.791 17.07 0.64 13.07 0.490
QD PL
color-burst
5.27
0.198
Figure-14 color bars, s-video Chrominance PAL-BDGNICc video output waveform
3U
HOL
U\
blank level
page 16 of 23
Century Semiconductor Inc.
Table-11 composite NTSC/PAL 525 Typical with 37.5 load, vref_o = vref_i, SETUP = 0 100% saturation color bars.
CS8552
Description
Peak C (high) White Burst (high) Black Blank Burst (low) Peak C (low) Sync
DAC data
488 400 171 136 114 57 48 0
Sync interval
0 0 0 0 0 0 0 1
mA V 32.55 1.221 26.68 1.000
100 IRE
PL
7.5 IRE
QD
400 370 321 291 245 215 166 136 114 blank level 40 IRE
11.41 0.423 9.07 0.34 7.6 0.285 3.8 0.00 0.143 0.00
3U
HOL
20 IRE 20 IRE
U\
sync level
page 17 of 23
Figure-15 colors, composite NTSC/PAL 525 video output waveform
Century Semiconductor Inc.
Table-12 composite PAL-BDGHINc 625 Typical with 37.5 load, vref_o = vref_i, SETUP = 0 100% saturation (100/0/100/0) color bars.
CS8552
Description
Peak C (high) White Burst (high) Black Blank Burst (low) Peak C (low) Sync
DAC data
488 400 171 136 114 57 48 0
Sync interval
0 0 0 0 0 0 0 1
mA V 32.88 1.233 26.68 1.000
PL
319
HOL
QD
400 368 284 236 204 152 120 black/blank level sync level Figure-16 Colors, composite PAL-BDGHINc 625 video output waveform
page 18 of 23
12.01 0.45 8.0 4.0 1.8 0.00 0.30 0.15 0.068 0.00
3U
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Century Semiconductor Inc.
RECOMMENDED OPERATING CONDITIONS Symbol VAA TA RL VREF_IN Power Supply Ambient Operating Temperature DAC Output Load External Voltage Reference Nominal REST 1.11 Parameter Min 3.0 0 Typ 3.3 37.5 1.23 850 Max 3.6 70 -1.35
CS8552
Unit V C V
ABSOLUTE MAXIMUM RATINGS
VAA TA
Power Supply (Measured to ground) Ambient Operating Temperature Voltage on Any Signal Pin
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---55 -GND-0.3 -65
Symbol
Parameter
Min
Typ
Max 5 125
Unit V C V C C
TS TJ
Storage Temperature Junction Temperature
QD
VAA+0.3 +150 +150
3U
HOL
page 19 of 23
PL
Century Semiconductor Inc.
DC CHARACTERISTICS
CS8552
(Recommended operating conditions using external voltage reference with RSET = 850, VREFIN = 1.23V, NTSC CCIR601 operation and clock frequency = 27MHz at 25C, +3.3V) Symbol IAA Parameter VAA Supply Current Video D/A Resolution INL DNL Integral Nonlinearity Differential Nonlinearity Maximum Output Current VOC Output Compliance Video level Error Full-Scale DAC Output Digital Inputs VIH VIL IIH IIL Input High Voltage Input Low Voltage Input High current (Vin=2.4V) Input Low current (Vin=0.4V) Digital Outputs VOH VOL IOZ VREF_IN 0 9 9 Min Typ Max 105 9 1 1 35 1.5 5 Unit mA Bits LSB LSB mA V % IRE
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182.5
QD
GND-0.3 2.4 10 1.23 10 1.11
2.0
VAA+0.3 0.8 1 -1
V V A A
PL
Output High Voltage (IOH=-400A) Output Low Voltage (IOL=3.2mA) Three-State Current
V 0.4 50 V A A 1.35 V A
VREF_OUT VREF_OUT Output Voltage IREF_OUT VREF_OUT current
3U
HOL
VREF_IN Input Current
page 20 of 23
Century Semiconductor Inc.
AC CHARACTERISTICS
CS8552
(Recommended operating conditions using external voltage reference with RSET = 850, VREFIN = 1.23V, NTSC CCIR601 operation and clock frequency = 27MHz at 25C, +3.3V) Symbol Parameter Luminance Bandwidth Chrominance Bandwidth Differential Gain Differential Phase SNR Hue Accuracy Color Saturation Accuracy 4 Analog Output Delay Analog Output Rise Time Analog Output Setting Time 1 2 3 Fck Pixel/Control Setup Time Pixel/Control Hold Time Control Output Delay Time CLOCK Frequency Min Typ Fck/4 1.3 1 1 60 1.5 3 3 Max Unit MHz MHz % dB % ns ns ns ns ns ns 29.5 MHz ns ns
QD
1 3 24.54 10 10
CLOCK Pulse Width Low Time
CLOCK Pulse Width High Time
3U
HOL
page 21 of 23
PL
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30 3 30 15 27
1.5
Century Semiconductor Inc.
Video Input and Output Timing
CS8552
CLOCK P[7:0] HSYNCN, VSYNCN (slave mode) HSYNCN, VSYNCN (master mode)
3 4 pixel 1 pixel 0 1 2 pixel 0 pixel 1
Analog output
Figure-17 Video Input and Output Timing
3U
HOL
page 22 of 23
PL
QD
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Century Semiconductor Inc.
PACKAGE OUTLINE (32-pin PLCC)
D D1
4 1 32 30
CS8552
A3
5
PIN 1 IDENTIFIER
29
E2
E1 E
13
21
14
20
A1
e D2
HOL
Dimensions in Millimeters NOM 2.79 REF 2.29 12.45 11.43 5.21 REF 14.99 13.97 6.48 REF 1.27 REF - MIN 0.50 0.20 1.91 0.40 0.66 12.32 11.35 14.86 13.89 0 10
PL
b b1 D2
Symbol A A1 A2 A3 A4 b b1 D D1 D2 E E1 E2 e
QD
A2 A
3U
MAX 3.56 -
U\
A4
E2
Dimensions in Inches MIN 0.020 0.008 0.075 0.016 0.026 0.485 0.447 0.585 0.547 NOM 0.110 REF 0.090 0.490 0.450 0.205 REF 0.590 0.550 0.255 REF 0.050 REF - MAX 0.14 0.014 0.095 0.021 0.032 0.495 0.453 0.595 0.553
0.35 2.41 0.53 0.81 12.57 11.51 15.11 14.05
0
10
page 23 of 23

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